1. Technical Field
The present disclosure relates to a method of manufacturing a non-volatile memory device, and more particularly, to a method of manufacturing a flash memory device having a tunnel insulation layer.
2. Description of the Related Art
Semiconductor memory devices, in general, are classified as either volatile or non-volatile memory devices. Volatile memory devices such as, for example, dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices have relatively high input/output (I/O) speeds, and may lose data stored therein when power is shut off. In contrast, non-volatile memory devices such as, for example, read-only memory (ROM) devices have relatively slow I/O speeds, and may be able to maintain data stored therein even when the power is shut off. Additionally, the demand for non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM) devices or flash EEPROM devices is increasing.
In a flash EEPROM device, data is electrically stored, e.g., programmed or erased, through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism. The flash memory device are generally classified as either a floating gate type or a charge trap type such as, for example, silicon-oxide-nitride-oxide semiconductor (SONOS) devices or metal-oxide-nitride-oxide semiconductor (MONOS) devices.
The floating gate type flash memory device typically includes a gate structure and source/drain regions on a semiconductor substrate. The gate structure includes a tunnel insulation layer, a floating gate electrode, a blocking layer and a control gate electrode. The tunnel insulation layer includes a silicon oxide layer formed by a thermal oxidation process, and the blocking layer includes a dielectric multilayer in which a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer are sequentially stacked. The floating gate electrode and the control gate electrode comprise polysilicon doped with impurities.
The charge trap type flash memory device includes a tunnel insulation layer on a channel region of a semiconductor substrate, a charge trapping layer for trapping electrons from the channel region, a blocking layer on the charge trap layer, and a gate electrode on the dielectric layer and spacers on sidewalls of the gate electrode.
The operation of the flash memory device includes stable repetition of charging and discharging electrons through the tunnel insulation layer, and thus electronic characteristics of the tunnel insulation layer may have a significant effect on the reliability of the flash memory device. For that reason, various types of research have been performed on improving the electronic characteristics of the tunnel insulation layer.
Injection of nitrogen (N) into a silicon oxide layer is generally known to minimize layer failures, such as layer defects or trap sites, because silicon (Si) atoms of the silicon oxide layer are chemically combined with nitrogen (N) atoms. Further, electrical shocks to the silicon oxide layer are also minimized in the charging and discharging of the electrons through the tunnel insulation layer because the bond energy of silicon (Si) and nitrogen (N) is much greater than that of silicon (Si) and oxygen (O). To inject nitrogen (N) atoms into a silicon oxide layer, a nitric oxide (NO) heat treatment process is typically performed on the silicon oxide layer after completing the formation of the silicon oxide layer.
However, the NO heat treatment after the formation of the silicon oxide layer distributes the nitrogen (N) atoms around a top surface of the silicon oxide layer, to thereby cause non-uniformity of nitrogen (N) atoms in a vertical direction through the silicon oxide layer. The non-uniformity of nitrogen (N) atoms through the silicon oxide layer may deteriorate the electrical characteristics of the tunnel insulation layer, which in turn may cause, for example, room temperature charge loss, thereby resulting the deterioration of the reliability of the flash memory device.